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DS1338 I C RTC with 56-Byte NV RAM
2
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GENERAL DESCRIPTION
The DS1338 serial real-time clock (RTC) is a lowpower, full binary-coded decimal (BCD) clock/calendar plus 56 bytes of NV SRAM. Address and data are transferred serially through an I2C interface. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1338 has a built-in powersense circuit that detects power failures and automatically switches to the backup supply, maintaining time and date operation
FEATURES
RTC Counts Seconds, Minutes, Hours, Date of the Month, Month, Day of the Week, and Year with Leap-Year Compensation Valid Up to 2100 Available in a Surface-Mount Package with an Integrated Crystal (DS1338C) 56-Byte Battery-Backed General-Purpose RAM with Unlimited Writes I2C Serial Interface Programmable Square-Wave Output Signal Automatic Power-Fail Detect and Switch Circuitry -40C to +85C Operating Temperature Range Underwriters Laboratory (UL) Recognized

APPLICATIONS
Handhelds (GPS, POS Terminal) Consumer Electronics (Set-Top Box, Digital Recording, Network Appliance) Office Equipment (Fax/Printer, Copier) Medical (Glucometer, Medicine Dispenser) Telecommunications (Router, Switcher, Server) Other (Utility Meter, Vending Machine, Thermostat, Modem)
ORDERING INFORMATION
PART DS1338Z-18+ DS1338Z-3+ DS1338Z-33+ DS1338U-18+ DS1338U-3+ DS1338U-33+ TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 8 SO (0.150) 8 SO (0.150) 8 SO (0.150) 8 SOP 8 SOP 8 SOP TOP MARK DS1338-18 DS1338-3 DS133833 1338 rr-18 1338 rr-3 1338 rr-33 DS1338C-18
TYPICAL OPERATING CIRCUIT
RPU = tr/Cb
VCC CRYSTAL RPU
VCC
VCC
RPU
X1 SCL CPU SDA
X2
VCC SQW/OUT
i
DS1338
GND VBAT
-40C to +85C 16 SO (0.300) DS1338C-3# -40C to +85C DS1338C-3 16 SO (0.300) DS1338C-33# -40C to +85C DS1338C-33 16 SO (0.300) rr = second line, revision level + Denotes a lead(Pb)-free/RoHS-compliant device. # Denotes a RoHS-compliant device that may include lead that is exempt under the RoHS requirements. The lead finish is JESD97 category e3, and is compatible with both lead-based and lead-free soldering processes. A "+" anywhere on the top mark denotes a lead-free device. A "#" denotes a RoHS-compliant device.
DS1338C-18#
Pin Configurations appear at end of data sheet.
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DS1338 I2C RTC with 56-Byte NV RAM
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground.........................................................................-0.3V to +6.0V Operating Temperature Range............................................................................................-40C to +85C Storage Temperature Range.............................................................................................-55C to +125C Soldering Temperature.........................See precautions in the Handling, PCB Layout, and Assembly Section.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER Supply Voltage Logic 1 Logic 0 Power-Fail Voltage VBAT Input Voltage SYMBOL VCC VIH VIL VPF VBAT CONDITIONS DS1338-18 DS1338-3 DS1338-33 (Note 2) (Note 2) DS1338-18 DS1338-3 DS1338-33 (Note 2) MIN 1.71 2.7 3.0 0.7 x VCC -0.3 1.51 2.45 2.70 1.3 1.62 2.59 2.82 3.0 TYP 1.8 3.0 3.3 MAX 1.89 3.3 5.5 VCC + 0.3 +0.3 x VCC 1.71 2.70 2.97 3.7 UNITS V V V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER Input Leakage I/O Leakage SDA Logic 0 Output SYMBOL ILI ILO IOLSDA CONDITIONS (Note 3) (Note 4) VCC > 2V; VOL = 0.4V VCC < 2V; VOL = 0.2 x VCC VCC > 2V; VOL = 0.4V 1.71V < VCC < 2V; VOL = 0.2 VCC 1.3V < VCC < 1.71V; VOL = 0.2 VCC DS1338-18 DS1338-3 VCC 3.63V DS1338-33 3.63V < VCC 5.5V DS1338-18 DS1338-3 VCC 3.63V DS1338-33 3.63V < VCC 5.5V MIN TYP MAX 1 1 3.0 3.0 3.0 3.0 250 75 110 120 60 80 85 150 200 200 325 100 125 125 200 25 100 nA mA A UNITS A A mA
SQW/OUT Logic 0 Output
IOLSQW
Active Supply Current (Note 5)
ICCA
A
Standby Current (Note 6)
ICCS
A
VBAT Leakage Current (VCC Active)
IBATLKG
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DS1338 I2C RTC with 56-Byte NV RAM
DC ELECTRICAL CHARACTERISTICS
(VCC = 0V, TA = -40C to +85C, unless otherwise noted. Typical values are at VBAT = 3.0V, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER VBAT Current (OSC ON); VBAT = 3.7V, SQW/OUT OFF (Note 7) VBAT Current (OSC ON); VBAT = 3.7V, SQW/OUT ON (32kHz) (Note 7) VBAT Data-Retention Current (Osc Off); VBAT = 3.7V (Note 7) SYMBOL IBATOSC1 IBATOSC2 IBATDAT MIN TYP 800 1025 10 MAX 1200 1400 100 UNITS nA nA nA
AC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C) (Note 1) PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Condition Hold Time (Repeated) START Condition (Note 8) LOW Period of SCL Clock HIGH Period of SCL Clock Setup Time for Repeated START Condition Data Hold Time (Notes 9, 10) Data Setup Time (Note 11) Rise Time of Both SDA and SCL Signals (Note 12) Fall Time of Both SDA and SCL Signals (Note 12) Setup Time for STOP Condition Capacitive Load for Each Bus Line I/O Capacitance (SDA, SCL) Oscillator Stop Flag (OSF) Delay SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO CB CI/O tOSF CONDITION Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode (Note 12) (Note 13) (Note 14) 100 MIN 100 0 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0.6 4.7 0 0 100 250 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.6 4.0 400 10 300 1000 300 300 0.9 TYP MAX 400 100 UNITS kHz s s s s s s ns ns ns s pF pF ms
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DS1338 I2C RTC with 56-Byte NV RAM
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40C to +85C) (Note 1, Figure 1) PARAMETER Recovery at Power-Up (Note 15) VCC Fall Time; VPF(MAX) to VPF(MIN) VCC Rise Time; VPF(MIN) to VPF(MAX) SYMBOL tREC tVCCF tVCCR 300 0 MIN TYP MAX 2 UNITS ms s s
Warning: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Limits at -40C are guaranteed by design and not production tested. All voltages are referenced to ground. SCL only. SDA and SQW/OUT. ICCA--SCL clocking at max frequency = 400kHz. 2 Specified with the I C bus inactive. Measured with a 32.768kHz crystal attached to X1 and X2. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW ) of the SCL signal. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. CB--total capacitance of one bus line in pF. Guaranteed by design. Not production tested. The parameter tOSF is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V VCC VCC(MAX) and 1.3V VBAT 3.7V. This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay occurs.
Note 12: Note 13: Note 14: Note 15:
Figure 1. Power-Up/Power-Down Timing
VCC VPF(MAX) VPF(MIN) t VCCF t VCCR tREC
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID VALID
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DS1338 I2C RTC with 56-Byte NV RAM
Figure 2. Timing Diagram
Figure 3. Block Diagram
X1
CL
SQW/OUT 1Hz/4.096kHz/8.192kHz/32.768kHz MUX/ BUFFER
N
1Hz X2
"C" VERSION ONLY CL
Oscillator and divider CONTROL LOGIC
RAM (56 X 8)
VCC GND VBAT POWER CONTROL
DS1338
SCL SDA SERIAL BUS INTERFACE AND ADDRESS REGISTER
CLOCK, CALENDAR, AND CONTROL REGISTERS
USER BUFFER (7 BYTES)
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DS1338 I2C RTC with 56-Byte NV RAM
TYPICAL OPERATING CHARACTERISTICS
IBAT vs. VBAT
1250 1200 1150 SUPPLY CURRENT (nA)
(
V CC=0V RS1=RS0=1
ICC vs. VCC
250
SCL=400kHz
225
IBAT OSC2 SQWE = 1)
SUPPLY CURRENT (uA)
1100 1050 1000 950 900 850 800 750 700 650 600 550 1.3 1.8 2.3 2.8
200 175 150 125 100 75 50
IBATOSC1 (SQWE = 0)
SCL=SDA=0Hz
3.8 VBAT (V)
3.3
4.3
4.8
5.3
1.8
2.3
2.8
3.3 3.8 VCC (V)
4.3
4.8
5.3
IBAT vs. Temperature
VBAT = 3.0V
V CC=0V
Oscillator Frequency vs. Supply Voltage
32768.5
1000 950 900 SUPPLY CURRENT (nA) 850 800 750 700 650 600 -40 -20 0 20 40 TEMPERATURE (C) 60 80
SQWE=0 SQWE=1
32768.4 FREQUENCY (Hz)
32768.3
32768.2
32768.1
32768.0 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 Oscillator Supply Voltage (V)
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DS1338 I2C RTC with 56-Byte NV RAM
PIN DESCRIPTION
PIN 8 1 16 -- NAME X1 FUNCTION 32.768kHz Crystal Connections. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF. An external 32.768kHz oscillator can also drive the DS1338. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.
Note: For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.
2
--
X2
3
14
VBAT
4
15
GND
5 6
16 1
SDA SCL
7
2
SQW/OUT
Backup Supply Input for Lithium Cell or Other Energy Source. Battery voltage must be held between the minimum and maximum limits for proper operation. Diodes placed in series between the backup source and the VBAT pin may prevent proper operation. If a backup supply is not required, VBAT must be grounded. UL recognized to ensure against reverse charging when used with a lithium cell. For more information, visit www.maxim-ic.com/qa/info/ul. Ground. DC power is provided to the device on these pins. VCC is the primary power input. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected to the device and VCC is below VPF, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. Serial Data. Input/output pin for the I2C serial interface. It is an open drain output and requires an external pullup resistor. The pull up voltage may be up to 5.5V regardless of the voltage on VCC. Serial Clock. Input pin for the I2C serial interface. Used to synchronize data movement on the serial interface. The pull up voltage may be up to 5.5V regardless of the voltage on VCC. Square-Wave/Output Driver. When enabled and the SQWE bit set to 1, the SQW/OUT pin outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz, 32kHz). It is an open drain output and requires an external pullup resistor. Operates with either VCC or VBAT applied. The pull up voltage may be up to 5.5V regardless of the voltage on VCC. If not used, this pin may be left floating. Primary Power Supply. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected to the device and VCC is below VPF, reads and writes are inhibited. The backup supply maintains the timekeeping function while VCC is absent. No Connection. These pins are not connected internally, but must be grounded for proper operation.
8
3
VCC
--
4-13
N.C.
DETAILED DESCRIPTION
The DS1338 serial RTC is a low-power, full BCD clock/calendar plus 56 bytes of NV SRAM. Address and data are transferred serially through an I2C interface. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1338 has a built-in power-sense circuit that detects power failures and automatically switches to the VBAT supply.
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DS1338 I2C RTC with 56-Byte NV RAM
OPERATION
The DS1338 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code, followed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBAT, the device power is switched from VCC to VBAT when VCC drops below VPF. If VPF is greater than VBAT, the device power is switched from VCC to VBAT when VCC drops below VBAT. The oscillator and timekeeping functions are maintained from the VBAT source until VCC is returned to nominal levels. The block diagram (Figure 3) shows the main elements of the DS1338. An enable bit in the seconds register controls the oscillator. Oscillator startup times are highly dependent upon crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major contributors to long start-up times. A circuit using a crystal with the recommended characteristics and proper layout usually starts within 1 second.
POWER CONTROL
The power-control function is provided by a precise, temperature-compensated voltage reference and a comparator circuit that monitors the VCC level. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBAT, the device power is switched from VCC to VBAT when VCC drops below VPF. If VPF is greater than VBAT, the device power is switched from VCC to VBAT when VCC drops below VBAT. The registers are maintained from the VBAT source until VCC is returned to nominal levels (Table 1). After VCC returns above VPF, read and write access is allowed after tREC (Figure 1). On the first application of power to the device the time and date
registers are reset to 01/01/00 01 00:00:00 (MM/DD/YY DOW HH:MM:SS). The CH bit in the seconds register will be set to a 1.
Table 1. Power Control
SUPPLY CONDITION VCC < VPF, VCC < VBAT VCC < VPF, VCC > VBAT VCC > VPF, VCC < VBAT VCC > VPF, VCC > VBAT READ/WRITE ACCESS No No Yes Yes POWERED BY VBAT VCC VCC VCC
OSCILLATOR CIRCUIT
The DS1338 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 2 specifies several crystal parameters for the external crystal. Figure 3 shows a functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal with the specified characteristics.
Table 2. Crystal Specifications*
PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL fO ESR CL 12.5 MIN TYP 32.768 50 MAX UNITS kHz k pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
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DS1338 I2C RTC with 56-Byte NV RAM
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal frequency drift caused by temperature shifts creates additional error. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 4 shows a typical PC board layout for isolating the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information.
DS1338C ONLY
The DS1338C integrates a standard 32,768Hz crystal in the package. Typical accuracy at nominal VCC and +25C is approximately 10ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature.
Figure 4. Typical PC Board Layout for Crystal
LOCAL GROUND PLANE (LAYER 2)
X1
CRYSTAL
X2
GND
NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED AREA (UPPER LEFT-HAND QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE PACKAGE.
RTC AND RAM ADDRESS MAP
Table 3 shows the address map for the RTC and RAM registers. The RTC registers and control register are located in address locations 00h to 07h. The RAM registers are located in address locations 08h to 3Fh. During a multibyte access, when the register pointer reaches 3Fh (the end of RAM space) it wraps around to location 00h (the beginning of the clock space). On an I2C START, STOP, or register pointer incrementing to location 00h, the current time and date is transferred to a second set of registers. The time and date in the secondary registers are read in a multibyte data transfer, while the clock continues to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read.
CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. See Figure 6 for the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the BCD format. Bit 7 of Register 0 is the clock halt (CH) bit. When this bit is set to 1, the oscillator is disabled. When cleared to 0, the oscillator is enabled. The clock can be halted whenever the timekeeping functions are not required, which minimizes VBAT current (IBATDAT) when VCC is not applied. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any start or stop and when the register pointer rolls over to zero. The countdown chain is reset 9 of 16
DS1338 I2C RTC with 56-Byte NV RAM whenever the seconds register is written. Write transfers occur on the acknowledge from the DS1338. Once the countdown chain is reset, to avoid rollover issues the remaining time and date registers must be written within 1 second. The 1Hz square-wave output, if enabled, transitions high 500ms after the seconds data transfer, provided the oscillator is already running. The DS1338 runs in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit, with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). If the 12/24-hour mode select is changed, the hours register must be re-initialized to the new format. On an I2C START, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock continues to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read.
Table 3. RTC and RAM Address Map
ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H-3FH
Note: Bits listed as "0" always read as a 0.
BIT 7 CH 0 0 0 0 0 OUT
BIT 6
BIT 5 10 Seconds 10 Minutes AM/PM 10 Hour 0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION Seconds Minutes Hours
RANGE 00-59 00-59 1-12 +AM/PM 00-23 1-7 01-31 01-12 00-99 00H-FFH
Seconds Minutes 10 Hour 0 0 Date Month Year SQWE 0 0 RS1 RS0 Hour Day
12/24 0 0 0
10 Date 0 10 Month
Day Date Month Year Control RAM 56 x 8
10 Year 0 OSF
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CONTROL REGISTER (07H)
The control register controls the operation of the SQW/OUT pin and provides oscillator status. Bit # Name POR BIT 7 OUT 1 BIT 6 0 0 BIT 5 OSF 1 BIT 4 SQWE 1 BIT 3 0 0 BIT 2 0 0 BIT 1 RS1 1 BIT 0 RS0 1
Bit 7: Output Control (OUT). Controls the output level of the SQW/OUT pin when the square-wave output is disabled. If SQWE = 0, the logic level on the SQW/OUT pin is 1 if OUT = 1; it is 0 if OUT = 0. Bit 5: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time period and can be used to judge the validity of the clock and calendar data. This bit is edge triggered, and is set to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a STOP condition. The following are examples of conditions that may cause the OSF bit to be set: 1) The first time power is applied. 2) The voltage present on VCC and VBAT are insufficient to support oscillation. 3) The CH bit is set to 1, disabling the oscillator. 4) External influences on the crystal (i.e., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF to logic 1 leaves the value unchanged. Bit 4: Square-Wave Enable (SQWE). When set to logic 1, this bit enables the oscillator output to operate with either VCC or VBAT applied. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits. Bits 1 and 0: Rate Select (RS1 and RS0). These bits control the frequency of the square-wave output when the square-wave output has been enabled. The table below lists the square-wave frequencies that can be selected with the RS bits.
Square-Wave Output
OUT X X X X 0 1 RS1 0 0 1 1 X X RS0 0 1 0 1 X X SQW OUTPUT 1Hz 4.096kHz 8.192kHz 32.768kHz 0 1 SQWE 1 1 1 1 0 0
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I2C SERIAL DATA BUS
The DS1338 supports the I2C protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data is a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master device, which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1338 operates as a slave on the I2C bus. Within the bus specifications, a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The DS1338 works in both modes. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (Figure 5). Data transfer can be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
Figure 5. Data Transfer on I2C Serial Bus
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DS1338 I2C RTC with 56-Byte NV RAM Depending upon the state of the R/W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The master transmits the first byte (the slave address). Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave address). The slave then returns an acknowledge bit, which is followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge" is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first. The DS1338 can operate in the following two modes: 1) Slave receiver mode (write mode): Serial data and clock are received through SDA and SCL. An acknowledge bit is transmitted after each byte is received. START and STOP conditions are recognized as the beginning and end of a serial transfer. Hardware performs address recognition after reception of the slave address and direction bit (Figure 6). The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS1338 address--1101000-- followed by the direction bit (R/W), which, for a write, is 0. After receiving and decoding the slave address byte, the slave outputs an acknowledge on the SDA line. After the DS1338 acknowledges the slave address and write bit, the master transmits a register address to the DS1338. This sets the register pointer on the DS1338, with DS1338 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the DS1338 acknowledging each byte received. The register pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. 2) Slave transmitter mode (read mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. The DS1338 transmits serial data on SDA while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (Figure 7). The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS1338 address-- 1101000--followed by the direction bit (R/W), which, for a read, is 1. After receiving and decoding the slave address byte, the slave outputs an acknowledge on the SDA line. The DS1338 then starts transmitting data using the register address pointed to by the register pointer. If the register pointer is not set before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. The register pointer is incremented after each byte is transferred. The DS1338 must receive a "not acknowledge" to end a read.
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Figure 6. Data Write--Slave Receiver Mode

S
1101000 0 A
XXXXXXXX A
MASTER TO SLAVE SLAVE TO MASTER
XXXXXXXX A
XXXXXXXX A ... XXXXXXXX A P
S - START A - ACKNOWLEDGE (ACK) P - STOP
DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE)
Figure 7. Data Read (From Current Pointer Location)--Slave Transmitter Mode

S
1101000
1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A ... XXXXXXXX A P
MASTER TO SLAVE SLAVE TO MASTER
S - START A - ACKNOWLEDGE (ACK) P - STOP
A - NOT ACKNOWLEDGE (NACK)
DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK
Figure 8. Data Read (Write Pointer, Then Read--Slave Receive and Transmit

S
1101000
0A
XXXXXXXX A Sr
1101000 1 A

XXXXXXXX A
XXXXXXXX A
XXXXXXXX A ...
XXXXXXXX A P
S - START SR - REPEATED START A - ACKNOWLEDGE (ACK) P - STOP A - NOT ACKNOWLEDGE (NACK)
MASTER TO SLAVE SLAVE TO MASTER
DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK
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DS1338 I2C RTC with 56-Byte NV RAM
HANDLING, PCB LAYOUT, AND ASSEMBLY
The DS1338C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning should be avoided to prevent damage to the crystal. Exposure to reflow is limited to 2 times maximum. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All N.C. (no connect) pins must be connected to ground. The leaded 16-SO package may be reflowed as long as the peak temperature does not exceed 240C. Peak reflow temperature ( 230C) duration should not exceed 10 seconds, and the total time above 200C should not exceed 40 seconds (30 seconds nominal). The RoHS and lead-free/RoHS packages may be reflowed using a reflow profile that complies with JEDEC J-STD020. Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisturesensitive device (MSD) classifications.
PIN CONFIGURATIONS
TOP VIEW X1 X2 VBAT GND 1
DS1338
TOP VIEW VCC SQW/OUT SCL SDA
SCL SQW/OUT Vcc N.C. N.C. N.C. N.C. N.C.
DS1338C
SDA GND VBAT N.C. N.C. N.C. N.C. N.C.
8 7 6 5
2 3 4
SO, SOP
SO (300 mils)
CHIP INFORMATION
TRANSISTOR COUNT: 12,231 PROCESS: CMOS
THERMAL INFORMATION
PART 8 SO 8 SOP 16 SO THETA-JA (C/W) 170 229 73 THETA-JC (C/W) 40 39 23
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NUMBER 21-0041 8 SO S8+4 21-0036 U8+1 8 MAX 21-0042 16 SO W16-H2
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DS1338 I2C RTC with 56-Byte NV RAM
REVISION HISTORY
REVISION DATE DESCRIPTION Modified the Features bullet to indicate that battery-backed RAM has unlimited writes. Removed leaded part numbers from the Ordering Information table. Removed the pullup resistor voltage spec from the Recommended DC Operating Conditions table and added it to the pin descriptions. Updated the block diagram (Figure 3) to show that SQW is open drain. Added the initial POR state for time and date registers in the Power Control section. Added text to explain the use of the oscillator bit to control battery current in the Clock and Calendar section. PAGES CHANGED 1 1 2, 7 5 8 9
100108
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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c) 2008 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

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